Reliability Challenges of Large Organic Substrate with High-Density Fan-out Package

Fan-out packaging technology is one advanced packaging approach that has increasingly been adopted for networking, artificial intelligence, and high-performance computing applications. It enables multi-chip integration to interconnect different function chips resulting in a flexible and cost-effective package solution. As the chip integration becomes diverse, larger package size accommodate higher I/O pins is needed. In this paper, we discuss the reliability assessment of larger organic substrate with integrated fan-out chip for networking applications. The organic substrate stacks-up by ABF, E (Electrical Grade) & S (Standard) glass core and assemblies with a 7nm ASIC + 8 I/O chiplets integrated fan-out chip. The CTE (coefficient of thermal expansion) mismatch between different materials in the whole packaging structure can cause the device to warp and induce mechanical stresses that cause substrate ABF and trace crack. We will discuss the substrate solder mask and trace design to enhance overall package reliability by using finite element stress analysis. A robust large format multi-chip fan-out package was developed and validated through reliability testing.