A Logic-Process Compatible RRAM with 15.43 Mb/mm2 Density and 10years@150°C retention using STI-less Dynamic-Gate and Self-Passivation Sidewall

We have successfully demonstrated, for the first time, the STI-less dynamic-gate (DG) technique with self-passivation sidewall (SPS) enhanced RRAM cells on a commercial 40nm CMOS production platform. This achievement resulted in a record-density of 15.43 Mb/mm ² and a high retention of 10years@150°C. Through a comprehensive design-technology co-optimization (DTCO) process, we obtain significant improvements in various key characteristics, as evidenced by experimental results at both the wafer (12-inch) and chip (4K&1M) level. These improvements include improved memory window (>20μA), enhanced uniformity, extended retention (10years@150°C), and multilevel cell (MLC>3bit). This work indicates the potential of RRAM as embedded non-volatile memory (eNVM) in advanced technology node for consumer and industrial applications.