纳米片
制作
晶体管
CMOS芯片
场效应晶体管
材料科学
逻辑门
扩散
纳米技术
光电子学
物理
计算机科学
电气工程
算法
工程类
电压
病理
热力学
医学
替代医学
作者
K. Mumba,S. Cai,K. Kálna
标识
DOI:10.1109/nano54668.2022.9928725
摘要
A fabrication process of stacked n-type gate-all-around (GAA) triple nanosheet (NS) field-effect transistors (FETs) is modelled by the 3D Victory Process (TCAD by Silvaco). The modelling confirms that the NS FET process flow is highly compatible with the FinFET fabrication. To verify the accuracy of the process modelling, carrier transport in the NS FET is simulated by the 3D Victory Device using quantum corrected drift-diffusion. Simulated I D -V G characteristics at drain biases of 0.05 V and 0.7 V are in a very good agreement with experimental data, including the sub-threshold region. The 1st NS channel provides the largest contribution to current density, while additional channels still contribute by a good increase to current density. The stacked GAA NS FETs are proved to be the cost-effective and performance-fitting solution for the sub-5 nm CMOS technology nodes.
科研通智能强力驱动
Strongly Powered by AbleSci AI