Controlling the thin interfacial buffer layer for improving the reliability of the Ta/Ta2O5/Pt resistive switching memory

Thin metal interfacial layers (1-nm-thick Ti and Hf) were exploited as the appropriate interfacial layer for forming an interfacial (buffer) layer between the 10-nm-thick Ta2O5 resistance switching layer and the Ta electrode to enhance the switching cycle endurance and uniformity. The thin metal interfacial layers were in-situ oxidized to TiOx (x < 2) and HfO2 layers, respectively, during the ion beam sputter deposition on the Ta2O5 layer. Compared with the devices with no interfacial layers, the switching uniformity was improved for both interfacial layers, with Ti showing the greatest improvement. The switching cycle endurance was largely degraded for the HfO2 interfacial layer, whereas the TiOx interfacial layer greatly improved in such aspects. The appropriate level of Ti-O bond energy and an excessively high Hf-O bond energy were suggested as the main reasons for such a critical difference.