A high-voltage half-bridge gate drive circuit for GaN devices with high-speed low-power and high-noise-immunity level shifter

A high-voltage half-bridge gate drive circuit for E-mode GaN device with high-speed low-power and high-noise-immunity level shifter is proposed in this paper. It adopts digital-level detection concept by combining fast-slewing and output-maintain circuits in high noise environments to achieve both small response time and high dV sw/dt noise immunity. The proposed gate driver is fabricated in 0.5μm 80V HV CMOS process where the active area is 1699×1522μm2. Simulation and experimental results of the level shifter demonstrate that propagation delay is only about 1.618ns and dV sw/dt noise immunity is up to 50V/ns with a low FOM equal to 0.04ns/μm·V.