Improvement of Amorphous InGaZnO Thin-Film Transistor Reliability and Electrical Performance Using ALD SiO2 Interfacial Layer on PECVD SiO2 Gate Insulator

Insulator engineering is required to improve the reliability of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). Silicon dioxide (SiO $_{\text{2}}$ ), which is widely used as the gate insulator (GI), is mainly deposited using plasma-enhanced chemical vapor deposition (PECVD) owing to its high deposition rate and large-area deposition capability at a relatively low temperature. However, SiO $_{\text{2}}$ deposited by PECVD may contain high hydrogen content, and hydrogen within the IGZO film acts as an electron donor or passivates oxygen-related defects. Excessive hydrogen diffusion from PECVD SiO $_{\text{2}}$ to the IGZO film during GI deposition and postdeposition annealing often results in severe negative shift of the threshold voltage. In this article, we used PECVD SiO $_{\text{2}}$ insulator with an interfacial SiO $_{\text{2}}$ layer deposited by atomic layer deposition (ALD) to control the hydrogen diffusion flux while maintaining the defect passivation role of hydrogen and reducing electron trapping defects within the GI. Compared to a device with no interfacial layer, the IGZO device with the ALD interfacial layer improved field-effect mobility from 8.05 to 10.97 cm $^{\text{2}}$ /V $\cdot$ s and also improved positive and negative bias stress (NBS) reliability by 53.3% and 56.2%, respectively.