Background Calibration of Capacitor Mismatch and Gain Error in Pipelined-SAR ADC Using Partially Split Structure

A background calibration of bit weights (BW) for pipelined successive approximation register (SAR) analogue-digital-converter (ADC) is proposed. Capacitor mismatch and insufficient gain of inter-stage amplifier are lumped into BW deviation. The back-end SAR ADC is split to 2 identical ADCs. For some signal amplitude near the comparator thresholds, the back-end split ADCs calculate the BWs by subtracting the outputs of ADC. For other signal amplitude, it obtains the offset mismatch (OM) of the split ADC in the same way. The gain mismatch (GM) induced spur of the split ADCs, which is hard to calibrate, is broken down to the noise floor by randomly changing the operating order of the split ADCs. This background calibration improves spurious free dynamic range (SFDR) from 70 dB to 95 dB, and signal-to-noise and distortion ratio (SINAD) from 55 dB to 73 dB, respectively. Besides, the calibration scheme converges after only 5×104 cycles, thereby significantly saving convergence time.