A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

A 5Gbp/s mobile memory I/O interface at sub-1.0V supply voltage with Low Voltage-Swing Terminated Logic (LVSTL) using a VSSQ (Ground) termination and an adaptive reference voltage calibration scheme is presented. Power efficiency is 2.4mW/Gbps/pin in 20nm mobile DRAM process, which is 44% lower value than that of LPDDR3.