Education Abstract: Thermal Challenges and Mitigation in 3D DRAM

Novel memory technologies such as 3D-stacked DRAMs [2], offering substantial memory bandwidth, have been commercialised in an attempt to break the memory wall. High Bandwidth Memory (HBM) [2], a modern 3D DRAM standard providing bandwidth as high as 1 TBps, is used in modern GPUs and AI processors running memory-intensive workloads. The vertical integration leads to higher memory density, better performance due to short interconnect lengths, reduced power consumption, and smaller form factor. Figure 1 shows the architecture of 3D DRAM (HBM2E memory), consisting of two stacks (Stack 0 and Stack 1) with each stack comprising four DRAM dies stacked vertically. The DRAM dies are physically connected with fast through-silicon via (TSV) interconnect and micro-bumps. Each die supports two physical channels and each channel consists of several banks that are organised into rows and columns, similar to a conventional DRAM.