NMOS逻辑
PMOS逻辑
结温
门驱动器
CMOS芯片
绝缘体上的硅
模具(集成电路)
功率半导体器件
电气工程
MOSFET
材料科学
功率(物理)
电子工程
电压
计算机科学
工程类
晶体管
光电子学
硅
物理
量子力学
纳米技术
作者
Asif Faruque,Ayesha Hassan,Yuyang Wang,H. Alan Mantooth
标识
DOI:10.1109/wipda58524.2023.10382204
摘要
This paper presents the design, integration technique, and test results of a non-isolated single-channel gate driver for heterogeneous integration inside a SiC power module. In order to survive at the anticipated junction temperature, the driver is built on a 180 nm silicon-on-insulator (SOI) CMOS technology that can run safely up to 175 $^{\circ}C$. Multiple pull-up (PMOS) slices and pull-down (NMOS) slices arranged in parallel serve as the current sourcing and sinking components of the gate driver. Through a controller block, each slice can be independently turned on or off, allowing the gate driver’s driving strength to be adjusted. Such dynamic drive strength can be crucial to optimizing the SiC power die’s voltage overshoot and switching loss in power converter applications. Additionally, a die temperature monitoring circuit is integrated inside the gate drive chip. The packaging, module integration techniques, and power switching test results using the designed gate driver are also presented in this work.
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