Impact of Aspect Ratio and Interface Trap Charge on the Performances of Junctionless MOSFET-Based Adiabatic Logic Circuit

In this article, junctionless MOSFET-based adiabatic logic circuits have been analyzed in the subthreshold regime. The junctionless MOSFET has been calibrated on the basis of the experimental results, and then, the impact of the aspect ratio on the power, delay, and power delay product (PDP) has been investigated in depth. Besides, the impact of the interface trap charges (ITCs) is also discussed. The analytical modeling of the power and delay considering the ITC has also been detailed. SILVACO ATLAS has been used to simulate the junctionless MOSFET-based subthreshold adiabatic logic circuits and to validate the analytical models. The impact of the Schottky barrier on digital performances has also been shown here to present clear ideas.