Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology

Design-technology-co-optimization (DTCO) is essential in deep submicron technologies (e.g., 14nm and below) to co-optimize process technology and design rules and obtain more benefit from advanced node. As the process technology shrinks to deep submicron, the importance of back-end-of-line (BEOL) interconnect in a full chip design drastically grows since its less-than-micron width brings unexpected critical design rules that requires novel design techniques. In this paper, we provide a comprehensive survey on recent challenging issues and cutting-edge design methodologies for DTCO in deep submicron interconnect technology, which includes: offset assignment for pin accessibility; monolithic 3D integration; middle-of-line (MOL) utilization for routing; BEOL-aware representative critical path circuit synthesis; and buried power rail (BPR).