Research and FPGA Implementation of Convolutional Neural Network Accelerator

Compared with CPU and GPU, FPGA has high performance, low power consumption, and flexible deployment characteristics. Nowadays, the convolutional neural network (CNN) is updated rapidly, and using the high-level synthesis (HLS) technology to design CNN image recognition accelerators has high efficiency. However, the operating speed and the energy efficiency ratio (EER) of the existing CNN accelerators designed by HLS technology are relatively low. We designed an FPGA-based CNN accelerator using HLS technology, which further improved acceleration efficiency through pipeline optimization, perfect loop, and multiplication split operation. We also realized the custom reusing of intellectual property (IP) cores. The CNN accelerator is verified on an 8-bit LeNet-5 model, and it has a recognition accuracy rate of 97.95% on the MNIST dataset, a single recognition time of 21.5ms, and a platform power consumption of 1.965W. And it reduces the recognition time by at least 5ms compared with other existing works. Its energy efficiency ratio is 23.67(s • W) ^-1 , which is 2.3 times and 4 times that of ARM and CPU respectively. These reflect the advantages of the FPGA-based CNN image recognition accelerator in that it can be flexibly deployed and has a high energy efficiency ratio under limited deployment power consumption.