比较器
偏移量(计算机科学)
计算机科学
模
三角积分调变
管道(软件)
算法
逐次逼近ADC
自动增益控制
带宽(计算)
数学
离散数学
电气工程
放大器
工程类
电信
电压
程序设计语言
作者
Hongshuai Zhang,Yan Zhu,Chi-Hang Chan,Rui P. Martins
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2022-05-01
卷期号:57 (5): 1480-1491
被引量:4
标识
DOI:10.1109/jssc.2021.3111912
摘要
This article presents an inherent gain error-tolerant noise-shaping (NS) successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC). The architecture is hybrid with a pure passive-feedforward (FF) NS SAR ADC in the first stage of the pipeline, realizing an $N$ -0 (2-0) multistage NS sigma–delta (MASH). The $N$ th order from the first stage shapes not only the quantization error and comparator noise but also the interstage gain and nonlinearity error, which greatly relaxes the gain accuracy constraint in the conventional pipelined architecture. In addition to gain, a code-counter-based (CCB) background offset calibration is introduced to mitigate the interstage offset with low cost. The prototype further adopts partial interleaving in the first stage for high speed while sharing the integration capacitors in the feed-forward (FF) structure for a compact area. The 2-0 MASH runs at 400 MS/s and achieves 25-MHz bandwidth with 8 $\times $ OSR, consuming 1.26-mW power from a 1-V supply. Within a gain error range of −16% to +12%, the SNDR of the ADC deviates less than 3 dB from the nominal 75-dB SNDR. Fabricated in a 28-nm CMOS process, it exhibits a 178-dB Schreier figure of merit (FoM S ).
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