7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET

With the escalating demand of data-intensive applications such as artificial intelligence (AI) and high-performance computing (HPC), off-chip data transfer has become a critical bottleneck. Consequently, the data rate of wireline serial links has been propelled beyond 200Gb/s [1]–[2]. The large and complex packaging used in these links presents significant signal integrity challenges, primarily substantial channel loss and reflections. To mitigate these issues, sophisticated digital equalization techniques are required. For instance, the use of extended lengths of feed-forward equalization (FFE), floating taps for reflection cancellation, and maximum likelihood sequence detection (MLSD) within RX DSP are essential to address severe signal integrity impairments. Furthermore, the analog frontend must provide additional bandwidth and reduced noise impairments as the baud rate of transmitted and received signals is doubled. Aggressive design innovations in both analog frontend and DSP are imperative to achieve competitive performance, area, and power efficiency in a 200Gb/s link. This paper presents a 212.5Gb/s DSP-based PAM-4 transceiver, fabricated in 4nm FinFET technology, achieving 2.5e-6 BER over a channel with loss exceeding 50dB.