积分器
功勋
三角积分调变
带宽(计算)
CMOS芯片
跨阻放大器
物理
逐次逼近ADC
电子工程
放大器
计算机科学
电气工程
电压
运算放大器
电信
工程类
比较器
光电子学
作者
Zixuan Xu,Kai Xing,Yan Zhu,Rui P. Martins,Chi-Hang Chan
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2023-01-01
卷期号:: 1-12
标识
DOI:10.1109/jssc.2023.3344884
摘要
This article presents an excess loop delay compensation (ELDC) free 20 MHz bandwidth (BW) fourth-order continuous-time sigma-delta modulator (CT SDM) facilitated by a noise-shaping continuous-time successive-approximation register (NS CT-SAR) ADC. The modulator comprises a second-order single amplifier biquad (SAB) loop filter (LF) and a second-order NS CT-SAR with a passive integrator. The NS CT-SAR provides a stable second-order NS with a dedicated reset operation to ensure a robust input biasing for its CT interface. With ping-pong operation in the passive integrator, the delay of the 6b CT quantizer (QTZ) with 1b redundancy reduces to only one SA cycle, thus enabling the ELDC-free design. An ac-coupled negative-R is introduced to support the SAB integrator, which achieves low power and maintains a stable performance at band-edge input. The prototype is fabricated in 28-nm CMOS technology, occupying an active area of 0.037 mm $^{2}$ . It achieves 75.5-dB SNDR with 20 MHz BW at 750 MHz sampling frequency while consuming 2.78 mW from 1.5 to 1 V supply voltage. The proposed SDM yields a Walden figure-of-merit (FoMw) of 14.3 fJ/conversion step and a Schreier FOM (FoMS) of 174.1 dB, which are competitive among single loop architectures with similar sampling frequency and BW, while this design is ELDC-free.
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