Analytical Modelling of Nanoscale MOSFET Characteristics and Their Impact on Low-Power Nanoelectronics Devices

The rapid advancement in nanoelectronics has necessitated the development of precise analytical models for nanoscale MOSFETs, which are crucial components in modern low-power VLSI circuits. This study provides an in-depth analysis of the characteristic parameters of nanoscale MOSFETs, focusing on their impact on the performance and efficiency of VLSI circuits. The methodology involves the development of an analytical model that accurately predicts the threshold voltage, subthreshold swing, and drain-induced barrier lowering (DIBL) for MOSFETs with channel lengths below 10 nm. The model was validated using a dataset comprising various MOSFET designs, with the threshold voltage calculated as 0.4 V, the subthreshold swing as 65 mV/decade, and DIBL as 45 mV/V. Results demonstrate that the proposed model offers significant improvements in predicting the behavior of nanoscale MOSFETs, leading to enhanced power efficiency in VLSI circuits. The conclusions indicate that this model can be effectively integrated into the design of low-power nanoelectronic devices, providing a robust framework for future advancements in the field.