设计技术
静态随机存取存储器
计算机科学
逻辑门
编译程序
计算机体系结构
工程类
电子工程
系统工程
操作系统
作者
Taejoong Song,Hoon Jung,Gi–Young Yang,Hoyoung Tang,Hayoung Kim,Dong-Wook Seo,Hoonki Kim,Woojin Rim,Sanghoon Baek,Sangyeop Baeck,Jonghoon Jung
标识
DOI:10.1109/cicc53496.2022.9772784
摘要
3nm Gate-All-Around (GAA) technology is introduced to suggest the future of logic transistor with performance, power, and area (PPA) benefit. However, as with the recent advanced technologies, GAA technology also faces the potential challenges to overcome for the optimum PPA. Therefore, Design-Technology Co-Optimization (DTCO) has become more important than ever to maximize technology-to-design benefits of GAA. In this paper, the motivation of DTCO is presented by showing the successful design examples in advanced technologies. Then, the design techniques of standard cell and SRAM compiler are proposed based on DTCO to maximize the benefit of 3nm GAA technology.
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