与非门
计算机科学
CMOS芯片
建筑
闪光灯(摄影)
计算机体系结构
缩放比例
嵌入式系统
内存体系结构
过程(计算)
电子工程
计算机硬件
逻辑门
工程类
操作系统
艺术
几何学
数学
算法
视觉艺术
作者
Zongliang Huo,Wei Cheng,Simon X. Yang
标识
DOI:10.1109/vlsitechnologyandcir46769.2022.9830285
摘要
Xtacking® architecture in 3D NAND flash expands the capability to achieve faster I/O speed and higher bit density. In Xtacking® architecture, independent processing of array and CMOS wafers facilitates innovations in both process technologies and design architectures. While 3D monolithic + heterogeneous integration poses substantial challenges, advanced topography optimization and wafer stress management techniques are developed to achieve highly reliable array and CMOS technologies with mature yield. The innovative Xtacking® architecture unleashes scaling potential for 3D NAND, and paves the way for future applications such as integrated SSD and in-memory computing.
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