计算机科学
缓存污染
非统一内存访问
隐藏物
操作系统
缓存着色
嵌入式系统
延迟时间
PCI Express
可扩展性
指令预取
注册存储器
并行计算
缓存算法
CPU缓存
半导体存储器
内存控制器
数据采集
作者
William J. Starke,Jeffrey Stuecheli,David Daly,J. S. Dodson,Florian Auernhammer,Patricia Sagmeister,Guy L. Guthrie,Charles F. Marino,M. S. Siegel,B. Blaner
出处
期刊:IBM journal of research and development
[IBM]
日期:2015-01-01
卷期号:59 (1): 3:1-3:13
被引量:52
标识
DOI:10.1147/jrd.2014.2376131
摘要
In this paper, we describe the IBM POWER8™ cache, interconnect, memory, and input/output subsystems, collectively referred to as the “nest.” This paper focuses on the enhancements made to the nest to achieve balanced and scalable designs, ranging from small 12-core single-socket systems, up to large 16-processor-socket, 192-core enterprise rack servers. A key aspect of the design has been increasing the end-to-end data and coherence bandwidth of the system, now featuring more than twice the bandwidth of the POWER7® processor. The paper describes the new memory-buffer chip, called Centaur, providing up to 128 MB of eDRAM (embedded dynamic random-access memory) buffer cache per processor, along with an improved DRAM (dynamic random-access memory) scheduler with support for prefetch and write optimizations, providing industry-leading memory bandwidth combined with low memory latency. It also describes new coherence-transport enhancements and the transition to directly integrated PCIe® (PCI Express®) support, as well as additions to the cache subsystem to support higher levels of virtualization and scalability including snoop filtering and cache sharing.
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