Dielectric Integrations and Advanced Interface Engineering for 2D Field‐Effect Transistors

As silicon-based transistors approach their physical limits, the challenge of further increasing chip integration intensifies. 2D semiconductors, with their atomically thin thickness, ultraflat surfaces, and van der Waals (vdW) integration capability, are seen as a key candidate for sub-1 nm nodes in the post-Moore era. However, the low dielectric integration quality, including discontinuity and substantial leakage currents due to the lack of nucleation sites during deposition, interfacial states causing serious charge scattering, uncontrolled threshold shifts, and bad uniformity from dielectric doping and damage, have become critical barriers to their real applications. This review focuses on this challenge and the possible solutions. The functions of dielectric materials in transistors and their criteria for 2D devices are first elucidated. The methods for high-quality dielectric integration with 2D channels, such as surface pretreatment, using 2D materials with native oxides, buffer layer insertion, vdW dielectric transfer, and new dielectric materials, are then reviewed. Additionally, the dielectric integration for advanced 3D integration of 2D materials is also discussed. Finally, this paper is concluded with a comparative summary and outlook, highlighting the importance of interfacial state control, dielectric integration for 2D p-type channels, and compatibility with silicon processes.