A Locking Time Reduced PLL Reusing DCM Feedback Delay Tap in the FPGA Designs

PLLs always serve as a frequency synthesizer for a wide range of frequencies with low jitter. A charge pump PLL which has been applied in the FPGA designs with low locking time is proposed. To alleviate the requirements of fast settling and maintain low complexity, the design reused feedback delay taps of the Digital Clock Managers (DCMs) and a few logic cells. A fast-locking technique is introduced by quantizing the phase error to regulate the loop bandwidth with the aid of DCM feedback delay taps. A tunable CP with low current mismatch has been utilized to decode the phase error sequence. The proposed design with less circuit cost realizes a 4.3% reduction in settling time.