The Effect of Through-Silicon-Via Thermal Stress on Metal-Oxide-Semiconductor Field-Effect Transistor Properties Under Cooling to Ultra-Low Temperatures

The thermal through-silicon-via (TTSV) has a serious thermal stress problem due to the mismatch of the coefficient of thermal expansion between the Si substrate and filler metal. At present, the thermal stress characteristics and strain mechanism of TTSV are mainly concerned with increases in temperature, and its temperature range is concentrated between 173 and 573 K. By employing finite element analysis and a device simulation method based on temperature-dependent material properties, the impact of TTSV thermal stress on metal-oxide-semiconductor field-effect transistor (MOSFET) properties is investigated under cooling down from room temperature to the ultra-low temperature (20 mK), where the magnitude of thermal stress in TTSV is closely associated with the TTSV diameter and results in significant tension near the Cu-Si interface and consequently increasing the likelihood of delamination and cracking. Considering the piezoresistive effect of the Si substrate, both the TTSV diameter and the distance between TTSV and MOSFET are found to have more pronounced effects on electron mobility along [100] crystal orientation and hole mobility along [110] crystal orientation. Applying a gate voltage of 3 V, the saturation current for the 45 nm-NMOS transistor oriented along channel [100] experiences a variation as high as 34.3%. Moreover, the TTSV with a diameter of 25 μm generates a change in MOSFET threshold voltage up to -56.65 mV at a distance as short as 20 μm. The influences exerted by the diameter and distance are consistent across carrier mobility, saturation current, and threshold voltage parameters.