A novel 650 V snapback-free PMOS-RC-SJBT with low switching and reverse recovery losses

Abstract A novel 650 V Snapback-free Reverse-conducting Super-junction (SJ) insulated gate bipolar transistor (RC-SJBT) with low switching and reverse recovery loss is proposed and investigated in paper. In where, SJ pillar acts as the drift region, meanwhile PMOS and Schottky are combined on the cathode side. Under the action of SJ pillar, the snapback is effectively suppressed and V o n − E o f f trade-off of IGBT is also improved. The PMOS and Schottky combined structure enhances on-state carriers of IGBT meanwhile reduces hole injection efficiency during reverse recovery of freewheel diode, thus the reverse recovery switching loss ( E r e c ) of PMOS-RC-SJBT is reduced without sacrificing IGBT’s performance. Investigated by the TCAD tools, the total switching loss of PMOS-RC-SJBT is reduced by 51.2% from Con. RC-IGBT and 40.6% than the latest commercial RC-IGBT IKWH30N65WR6 of Infineon. Besides that, t s c is increased by 35.3% than RC-SJBT. Additionally, the snapback-free P-collector width is reduced from 340 µ m of Con.RC-IGBT to 40 µ m of PMOS-RC-SJBT, where the current uniformity is substantially improved.