Lift-off-Free Complementary Carbon Nanotube FETs Fabricated With Conventional Processing in a Silicon Foundry

We demonstrate complementary carbon nanotube (CNT) field-effect transistors (CNFETs) at the 90 nm node on 200 mm substrates within a commercial silicon foundry. This work advances beyond the state-of-the-art by (1) realizing complementary p- and n-type CNFETs and complementary (CMOS) CNFET logic based on a fully lift-off-free process (versus prior work that relied on non-conventional lift-off processing), (2) introducing an atomic layer deposited (ALD) protective interfacial metallic layer for improved metal-CNT source and drain contacts, and (3) show this process is VLSI-compatible and wafer-scale with improved yield, uniformity, and performance versus prior art. Importantly, these improvements enable CNFETs to be seamlessly integrated within existing silicon fabrication infrastructure, as it relies on only existing tooling currently used for silicon CMOS production, is low-temperature (≤415°C) and thus still back-end-of-line compatible, and is wafer-scale across industry-standard ≥200 mm substrates.