Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors

The benefits of applying the shallow trench isolation (STI) concept to a higher voltage thin-SOI laterally diffused metal oxide semiconductor (LDMOS) (in the range of 80 V) are analysed in this paper by means of 2D technology computer-aided design (TCAD) numerical simulations. The TCAD simulation results allow comparing the electrical performance of the studied STI LDMOS structure with that of a conventional LDMOS in terms of the main static (breakdown voltage (VBR) and specific on-state resistance (RON-sp)) and dynamic (gate–drain capacitance (CGD) and cut-off frequency (fT)) characteristics. Moreover, the impact of the STI length (LSTI) and thickness (TSTI), and the N-drift implantation energy on the electrical characteristics is considered in detail. On the other hand, the STI block helps to move the harmful high electric field further away from the silicon surface, thus minimizing gate–oxide degradation by hot carriers.