Functional Verification of MAC-PHY Layer of PCI Express Gen5.0 with PIPE Interface using UVM

Peripheral Component Interconnect (PCI) Express is a modern, high performance, point to point, general purpose input output interconnect communication protocol. PCI Express supersedes other legacy buses and provides higher bandwidth which makes it ideal choice for many applications. It provides layered architecture which contains three separate layers. Information flows among these layers in terms of packets. PCI Express Gen5.0 is a latest protocol which provides data rate of 32GT/s per lane and backward compatible with previous releases of PCI Express specifications Gen4.0(16GT/s), Gen3.0(8GT/s), Gen2.0 (5GT/s) and Gen1.1 (2.5GT/s). This presented paper performs the verification of the PCI Express Gen5.0 transactions between MAC (Media Access Layer) and PHY (Combination of SerDes & Physical Sub-block (Physical Media Attachment Layer)) layers of PCIe Gen5.0 physical layer. The RTL of PCI Express Gen5.0 is designed in SystemVerilog language and for the verification purpose, the methodology used is Universal Verification Methodology. Simulation results show the efficacy of the proposed procedure which are shown in Synopsys Discovery Visual Environment tool successfully.