Ultrathin interfacial SiO2 layer process research for high-k gate last gate stacks

Continued scaling of the gate dielectric has driven the adoption of high-k materials for the gate stack. A key challenge for enabling the adoption of these high-k materials is providing a SiO ₂ /SiON interfacial layer in a controlled and repeatable manner. Interfacial oxide is a buffer layer between silicon substrate and high-k dielectric, the role of the interfacial layer is to improve high-k dielectric/silicon substrate interface quality, the channel carrier mobility and act as the nucleation layer of high-k dielectric deposition, but reduced the EOT of gate stack. In this paper, based on radical oxidation (N ₂ O/H ₂ ) and spike dry-oxygen oxidation, we compared and studied several IL processes characteristics. According to the necessary of gate-last device, and the IL process space, we sought four better processes suitable for gate last device. Then we test the Dit and Qtot for the four processes and do comparative studied discussion. At last, we do repeatability test for a 3A recipe, data show the repeatability is very well. So through the extension of radial oxidation and spike oxidation, we can obtain the best interfacial process condition of gate last high-k gate stacks.