比较器
寄生提取
逐次逼近ADC
转换器
电子工程
电容器
计算机科学
噪声整形
噪音(视频)
堆积
无杂散动态范围
衰减
功率(物理)
电气工程
工程类
物理
CMOS芯片
光学
核磁共振
量子力学
电压
人工智能
图像(数学)
作者
Xingshuai Zou,Jiaxin Liu,Qiang Li
出处
期刊:Authorea - Authorea
日期:2023-02-12
标识
DOI:10.22541/au.167621583.32115149/v1
摘要
The fully passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) are simple, OTA-free and scaling friendly. Previous passive NS-SAR ADCs rely on the multi-path-input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high-order systems. This work proposes a new fully passive NS-SAR technique, it can realize 2× gain with a simple structure, leading to the reduced comparator power and less parasitics. This technique is also easy to extend to high-order NS-SAR ADCs.
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