Integrated transfer of large-scale gate dielectric/2D material films for low-power devices

With silicon-based devices nearing the limits of physical miniaturization, the hunt for alternative electronic materials is more critical. Two-dimensional (2D) semiconductors stand out as compelling candidates for future research, owing to their simple vertical integration, efficient carrier modulation, and good compatibility with complementary metal–oxide–semiconductor technology. However, 2D materials with atomic thickness are usually too fragile to maintain their inherent characteristics in the device manufacturing process; thus, interface engineering is crucial to achieve high-performance transistor arrays. In this research, we introduce a damage-free integrated transfer technique for centimeter-scale gate dielectric/2D material stacks, leveraging a water-assisted approach. This method is capable of transferring dielectric layers as thin as 4 nm with exceptional surface smoothness of less than 0.3 nm. The fabrication of MoS2 top-gate transistors with atomically clean and electronically sharp interfaces has resulted in remarkable device performance, including mobility of ∼34 cm2/(Vs), an on/off ratio exceeding 106, and a subthreshold swing as low as 72 mV/dec. Extensive statistical analysis of these large-area devices confirms the potential for high-uniformity, low-power device fabrication. Moreover, the scalability of this technique to various nanomaterials holds promise for advancing large-area damage-free transfer processes and the development of high-performance gate arrays.