扇出
薄脆饼
晶圆级封装
有限元法
过程(计算)
机械工程
计算机科学
工程类
电子工程
结构工程
电气工程
操作系统
作者
Cheng Chen,Daquan Yu,Teng Wang,Zhiyi Xiao,Lixi Wan
出处
期刊:IEEE Transactions on Components, Packaging and Manufacturing Technology
[Institute of Electrical and Electronics Engineers]
日期:2019-05-01
卷期号:9 (5): 845-853
被引量:24
标识
DOI:10.1109/tcpmt.2019.2907295
摘要
The fan-out package is designed to provide increased I/O density within a reduced form factor at a lower cost, as well as good electrical performance and heterogeneous integration capabilities, which has gained significant attention in recent years. However, warpage control during manufacturing process is a key character for fan-out packages. This paper focuses on the warpage prediction and optimization of embedded silicon fan-out (eSiFO) wafer-level package. An extended theoretical calculation model is applied and demonstrated, and the effects of various parameters on warpage were analyzed for optimization. By comparison with the experimental results, the finite-element modeling (FEM) simulation results and classic bimaterial model, the proposed extended theoretical calculation model is proven to be simple, fast, and effective for eSiFO wafer-level package. The effects of process steps, structural parameters, and material parameters were studied based on the extended theoretical model, and some advice on reducing warpage was given in the end. This paper offers an insight work for the warpage study of other embedded and fan-out packages.
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