纳米片
计算机科学
块(置换群论)
集成电路布局
互连
标准电池
节点(物理)
材料科学
布线(电子设计自动化)
缩放比例
超大规模集成
水准点(测量)
集成电路设计
纳米技术
嵌入式系统
电子工程
工程类
集成电路
电信
数学
操作系统
结构工程
地理
大地测量学
几何学
作者
Taehak Kim,Joohee Jeong,Seungmin Woo,Jeonggyu Yang,Hyun Woo Kim,Ahyeon Nam,Changdong Lee,Jinmin Seo,Minji Kim,Siwon Ryu,Yoonju Oh,Taigon Song
出处
期刊:IEEE Transactions on Very Large Scale Integration Systems
[Institute of Electrical and Electronics Engineers]
日期:2023-02-01
卷期号:31 (2): 163-176
标识
DOI:10.1109/tvlsi.2022.3229442
摘要
Nanosheet FETs (NSFETs) are attracting attention as promising devices that can replace FinFETs beyond the 5-nm node. Despite the importance of the devices, few studies analyze the impact of NSFETs at the block-level. In this article, we introduce NS3K, the first 3-nm NSFET standard cell library, and examine the results on a block-level scale. In addition to the overall process of designing a full library, we extended the scope of the buried power rail (BPR) to better layout designs. We showed that BPR, originally proposed to overcome power delivery problems, is also an effective solution for standard cell hegith reductions. Using BPR, we highlight that 4-track height standard cell designs have a negligible impact on power delivery and signal routing. Overall chip results show that the 3-nm NSFET outperforms the 5-nm FinFET by −27.4% in power, −25.8% in total wirelength, −8.5% in the number of cells, −47.6% in area, and 34.7% performance, respectively, owing to better device performance and interconnect scaling. However, careful device/layout designs and new interconnect structures must be applied to continue the scaling trend and maximize the advantages of 3-nm technology.
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