A low power 1.25fJ/conv-step 12-bit SAR ADC with a high-efficient Dynamic Comparator

This paper describes the design of a low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The high resolution and the low reference voltage pose challenges in the comparator design as ultra-low power consumption is required. A novel comparator scheme with two stages dynamic pre-amplifier is proposed. The entire ADC uses a 65nm CMOS process. The low-power 12-bit SAR ADC occupies an area of 412.45 $\mu{m}\times$ 440.36$\mu$m. Simulation results show that the ADC, at 12 bit, 1.8 MS/s, achieves a Nyquist signal-to-noise-and-distortion ratio (SNDR) of 73.52 dB, a spurious-free dynamic range (SFDR) of 91.6 dB while dissipating 8.68 $\mu$W from a 0.9V supply. The effective number of bits (ENOB) is 11.92-bit. The figure of merit (FOM) is 1.25fJ/conv-step.