Enabling low-power analog and RFIC design through advanced semiconductor FDSOI MOSFETs

Abstract This study investigates the electrical performance of advanced semiconductor Ge-pocket-doped fully depleted silicon-on-insulator MOSFETs in comparison to conventional fully depleted silicon-on-insulator (FDSOI) MOSFETs. In this study vital electrical parameters such as the drain current, band diagram, lateral electric field, surface potential, and work function of the gate material were investigated. The advanced Ge pocket-doped FDSOI MOSFET structure demonstrates superior characteristics, such as a higher I on /I off ratio, smaller subthreshold slope, lower capacitance, and higher cut-off frequency, when compared to conventional FDSOI MOSFETs. The structure of the Ge pocket-doped FDSOI MOSFET in the source and drain regions is designed to overcome the scaling effects of the transistor. In addition, this paper delves into the fabrication of the proposed device structure, outlining the key steps and intricacies involved. This study shows that the proposed device can be used for both digital and analog applications because it has good switching performance and a low cut-off frequency. In addition, the fabrication steps of the proposed structure were compatible with the existing fabrication process steps for conventional FDSOI MOSFETs. The simulation and analysis of the advanced semiconductor structure were performed using the Sentaurus TCAD simulator.