Leakage Reduction of GAA Stacked SI Nanosheet CMOS Transistors and 6T-SRAM Cell Via Spacer Bottom Footing Optimization

In this work, the significant leakage reduction approach is proposed and investigated by critical spacer bottom footing (SBF) optimization for gate-all-around (GAA) stacked Si nanosheet (SiNS) transistors. The fabricated GAA stacked SiNS CMOS transistors and standard 6T static random-access memory (SRAM) cell have achieved reduced static-state leakage current by an order of magnitude and improved read static noise margin (RSNM) by +12.67% due to SBF optimization. The performance boosting origins from improving the gate and source/drain overlap doping profile via SBF optimization, and thus suppressing the band to band tunneling leakage current correspondingly. The proposed leakage reduction approach can inspire and broaden the ultralow power performance application for the state-of-the-art GAA nanosheet technology.