Impacts of RTP Pyrometer Offsets on Wafer Overlay Residue

Throughout the history of rapid thermal process (RTP), the solution to wafer distortion has been a focused issue of researchers. RTP featuring high temperatures, fast ramp rates and high strain rates always results in the deformation of the silicon wafer substrate, which in turn causes lithographic overlay errors. This problem has become more and more serious in recent years as wafer size keeps increasing and device geometry continues shrinking. Even though a number of events have been documented, an investigation of more subtle correlation between overlay failure and RTP is in urgent requirement. Herein, the effects of RTP process conditions on overlay accuracy in the fabrication of 55 nm e-flash memory gate dielectric were studied. Results from this investigation demonstrated that pyrometer offsets at wafer edge influence overlay residue significantly. The overlay vectors shrink with the decrease of pyrometer offset delta between probe seven and probe six. Moreover, this offset delta had to be controlled between 2.5 °C to 4 °C in order to ensure the oxide thickness uniformity and tolerable overlay residue.