A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET

A low-power transceiver using a flexible clocking scheme is presented to enable the entire range of rates for Ethernet and PCIe applications. In addition, each lane can independently support any data rate within the same protocol. Implemented in 5nm FinFET, the quad transceiver occupies 1806×825μm ² and achieves a total power efficiency of 5.6pJ/b per lane including analog and DSP at 112Gb/s.