争先恐后
算法
校准
计算机科学
抖动
dBc公司
数学
统计
程序设计语言
电信
偏移量(计算机科学)
作者
Qiaochu Zhang,Hsiang-Chun Cheng,Stephen Y. H. Su,Mike Shuo-Wei Chen
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2023-01-01
卷期号:: 1-12
标识
DOI:10.1109/jssc.2023.3320886
摘要
This article presents a fractional- N digital multiplying delay-locked loop (MDLL) that uses a digital-to-time converter (DTC) for controlling the reference injection timing to support the fractional- N operation. This fractional- N MDLL features an injection-error scrambling scheme for DTC error randomization and a background third-order DTC delay equalizer for DTC error calibration, to mitigate reference-injection-induced spurs while keeping a low phase noise floor. The MDLL prototype demonstrates 800-fs rms jitter, $-$ 67 dBc fractional spur, and $-$ 58 dBc reference spur. With the proposed schemes, the fractional and reference spurs are suppressed by 29 and 32 dB, respectively.
科研通智能强力驱动
Strongly Powered by AbleSci AI