Advanced 3D Packaging of 3.2Tbs Optical Engine for Co-packaged Optics (CPO) in Hyperscale Data Center Networks

This paper describes industry’s first 3.2Tbs optical engine with integrated mux-dmux on chip, used for co-packaged optics (CPO) application for high bandwidth switch networking systems. Cisco presents an advanced 3D packaging fanout technology that integrates photonic integrated circuits (PICs) and electrical ICs (EICs), allowing for a compact design and low parasitic electrical connectivity using wafer scale redistribution layers (RDLs). The paper discusses key technical challenges, such as managing heterogeneous layouts of silicon photonics and electrical ICs, designing & fabricating RDL interconnects between various chips, ensuring a seamless input-output (I/O) interface, achieving high density Application Specific Integrated Circuit (ASIC) connectivity, and enabling high channel density die-edge fiber array coupling. We will delve into the integration of packaging design, optimization of signal integrity, development of assembly processes, and control of warpage through different interconnect bonding methods, all of which culminated in a successful co-packaged optics switch system demonstration. This paper presents a reworkable approach for assembling multiple, high bandwidth optical engines on a large body organic substrate, as well as managing large body package warpage and surface mount assembly issues.