Ternary Transistors With Reconfigurable Polarities

Abstract The recent surge in interest in ultra‐power‐saving electronic systems has highlighted multi‐valued logic circuitry as a promising technology that can simultaneously reduce circuit area, complexity, and power consumption compared to conventional binary logic. Nevertheless, the development of both p ‐type and n ‐type multi‐valued transistors with stable intermediate states is rare, particularly without CMOS‐incompatible heterostructures. Here, polarity‐reconfigurable ternary transistors are introduced fabricated using few‐layer black phosphorus (BP) homojunction. The ternary transistors feature asymmetric contacts and control gates, which determine carrier polarity and injection levels. The control gates allow the conversion from a conventional ambipolar operation to a p ‐type ternary operation, with a ≈50‐fold improvement in the on–off ratio and a well‐defined intermediate state. The intermediate state is established by a weakly gate‐dependent injection of minority carriers. The operational characteristics are discussed in relation to the applied control gate, drain bias, BP thickness, and contact metal, along with the ternary‐to‐binary transition. Notably, the devices also exhibit electrical switching to an n ‐type ternary operation, with its intermediate state matching that of the p ‐type ternary operation thanks to the antisymmetric device architecture.