浅沟隔离
材料科学
氮化物
炸薯条
图层(电子)
氮化硅
化学机械平面化
光电子学
电子工程
沟槽
工程类
纳米技术
电气工程
作者
Jihong Choi,Shantanu Tripathi,David Hansen,David Dornfeld
出处
期刊:Laboratory for Manufacturing and Sustainability
日期:2006-02-01
摘要
CMP has been successfully used for shallow trench isolation (STI) process in front end semiconductor processing. In STI process, nitride covers active device area acting as the CMP stop layer. Amount of nitride erosion during CMP is directly related to the step height of oxide isolation structure after removing nitride, and affects device performance as well. As semiconductor technology node is decreasing beyond 90nm, variation of nitride erosion over a chip in CMP process should be controlled within tight specifications. A model based simulation tool for chip scale variation of nitride erosion would improve not only CMP compatible STI layout design but also help in optimization of high density plasma chemical vapor deposition (HDPCVD) process of oxide layer. In this paper, a chip scale modeling scheme for better prediction of nitride erosion map integrating HDPCVD oxide topography is presented. In addition, a simulation result for a specially designed test pattern resembling production level STI layout is presented.
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