A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm

This brief presents an output-capacitor-free Digital LDO (DLDO) with a novel synthesizable PID controller architecture. The architecture employs multiple asynchronous wave pipelines and a novel differential control loop in parallel with a synchronous fine control. The DLDO is fabricated in a 65nm process and occupies an area of 0.0925mm 2. The DLDO has an output current range of 5mA - 80mA at 50mV dropout and achieves a 93.3ps response time with 99.75% current efficiency resulting in a FOM of 233fs.