纳米片
临界尺寸
电子工程
功率(物理)
维数(图论)
计算机科学
逻辑门
低功耗电子学
缩放比例
材料科学
工程类
纳米技术
物理
数学
功率消耗
几何学
纯数学
光学
量子力学
作者
Ruqiang Bao,Reinaldo A. Vega,S. Pancharatnam,P. Jamison,M. Wang,N. Loubet,Veeraraghavan Basker,Daniel J. Dechene,Dechao Guo,B. Haran,H. Bu,Kôji Watanabe,Mukesh Khare,J. Zhang,Jong-Ru Guo,Huimei Zhou,Anny Gaul,M. Sankarapandian,J. Li,Alex Hubbard
标识
DOI:10.1109/iedm19573.2019.8993480
摘要
In Nanosheet (NS) device architecture, it is much more challenging than FinFET to develop a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement on the dimensions due to the critical dimension scaling and complex structure. In this abstract, we reported an innovative integration scheme to enable volumeless multi-Vt and metal multi-Vt to provide the multi-Vt solutions in NS technology for high performance computing (HPC) and low-power applications. We developed a new volumeless multi-Vt for NS to solve the device geometry constraint and offer more margin and the opportunity for further sheet-to-sheet spacing (Tsus) reduction. Furthermore, metal gate boundary control (MGBC) was developed to enable variable NS widths on the same wafer to satisfy both HPC and low-power applications.
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