Ka-Band Three-Stacked CMOS Power Amplifier With LC Shunt-Feedback to Enhance Gain and Stability

In this brief, we designed a Ka-band three-stacked CMOS power amplifier (PA) to obtain high output power. Due to the positive feedback path attributed to the complexity of the three-stacked power stage layout, typical capacitive neutralization techniques alone are insufficient to achieve high gain and stability at the same time. To solve this problem, we proposed an LC shunt-feedback technique that can alleviate performance degradation caused by parasitic inductance in the gate node of a power transistor. We designed a PA using a 65-nm RFCMOS process to verify the utility of the proposed structure. At 38 GHz, the proposed PA achieves output 1-dB compression point (OP1dB) of 18.8 dBm, saturation output power (PSAT) of 22.0 dBm, peak power-added efficiency (PAE) of 21.9%, and small signal gain of 32.2 dB, respectively. The PA is measured with 64-quadrature amplitude modulation (QAM) signals, which has a 100-MHz channel bandwidth and a 9.7-dB peak-to-average power ratio (PAPR). At 38GHz, the PA achieves output power of 13.8-dBm with −25-dB error vector magnitude (EVM) and the adjacent channel leakage ratio (ACLR) of −28.1 dBc, respectively. The chip and core sizes of the power amplifier are $0.342~{\mathrm{ mm}}^{2}$ and 0.096 mm2, respectively.