A robust shallow trench isolation (STI) with SiN pull-back process for advanced DRAM technology

In this paper, the effect of SiN pull-back process for shallow trench isolation (STI) is investigated by measuring DRAM array's refresh time (Tref) and yield as sensitive monitors. The SiN pull-back is performed by using H/sub 3/PO/sub 4/ solution after trench etch (i.e. before liner oxidation). For comparison, DRAMs were fabricated by using various isolation methods including LOCOS, conventional STI, and poly-buffered STI (PB-STI). The SiN pull-back process is known for reducing divot around the top comer in conventional STI. Both LOCOS and PB-STI can result in divot free. It is also known that divot will degrade the inverse narrow width effect of pass transistor and result in double hump. In our study, SiN pull-back in STI indeed eliminates double-hump in I/sub d/-V/sub g/ curves of pass transistors. The SiN pull-back also can result in better data retention of DRAM than if without pull-back, but comparable to LOCOS and PB-STI. The optimized window of SiN pull-back in this study is 10 nm to 40 nm with best yield at 15 nm (slightly better yield than LOCOS and PB-STI).