PMOS逻辑
堆栈(抽象数据类型)
材料科学
硅锗
光电子学
逻辑门
工程物理
电子工程
电气工程
计算机科学
工程类
晶体管
硅
电压
程序设计语言
作者
Pouya Hashemi,Takashi Ando,E. Cartier,Kam‐Leung Lee,J. Bruley,Choong‐Hyun Lee,V. Narayanan
标识
DOI:10.1109/iedm.2017.8268510
摘要
Strained-SiGe, with high-Ge-content, has recently drawn significant attention as an alternate p-channel option for advance FinFETs. Among various technological challenges, gate stack is so critical to enable high-performance FETs. In this paper, key process details of the optimized gate stacks in high-Ge SiGe, such as IL formation and passivation, are disclosed and feasibility of Vth tuning by an ultra-thin replacement metal-gate scheme down to 15nm LG is demonstrated, for the first time. Moreover, near ideal SS, excellent reliability and mobility at scaled EOTs are achieved, which has led to high transconductance devices with proper junction engineering. In addition, we demonstrate the most aggressively-scaled SiGe fins reported to date formed by 3D-Ge-condensation, exhibiting excellent short-channel characteristics.
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