Lv56
1528 积分 2023-11-22 加入
A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS
4天前
已关闭
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection
10天前
已完结
A 0.5-0.8V 10-85 MS/s 12-Bit SAR ADC in 22nm FDSOI Utilizing an Inverter-Based Comparator Architecture
10天前
已完结
A Sub-7-GHz Linear Receiver for 5G Local Area Base Station Applications
10天前
已完结
Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS
11天前
已完结
60 GHz 7-Bit Passive Vector-Sum Phase Shifter With an X-Type Attenuator
11天前
已完结
Design Considerations of High- Frequency-Reference Fractional- N PLL: Architecture and Nonidealities
14天前
已完结
A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm
14天前
已完结
A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise
14天前
已完结
An FBAR Driven −261dB FOM Fractional-N PLL
14天前
已完结
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