Lv51
965 积分 2021-06-04 加入
1.25Gb/s low jitter dual-loop clock and data recovery circuit
1个月前
已完结
Design of an Auto-Negotiation Logic for SGMII Applications
1个月前
已完结
A 23mW/lane 1.2–6.8Gb/s multi-standard transceiver in 28nm CMOS
1个月前
已完结
An Integrated LVDS Transmitter in 0.18-$\mu$ m CMOS Technology With High Immunity to EMI
1个月前
已完结
Design of an EMI Self-Immune VML Transmitter in 0.18-$\mu$ m CMOS
1个月前
已完结
Design of a CML Transceiver With Self-Immunity to EMI in 0.18- $\mu $ m CMOS
1个月前
已完结
An Integrated LVDS Transmitter–Receiver System With Increased Self-Immunity to EMI in 0.18-um CMOS
1个月前
已完结
Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories
1个月前
已完结
Methodology for optimizing ESD protection for high speed LVDS based I/Os
1个月前
已完结
Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface
1个月前
已完结
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