Lv1
10 积分 2026-06-10 加入
A 3-nm FinFET CMOS PAM-4 Retimer for $\mathbf{8 0 0 - Gb} / \mathbf{s}$ and $\mathbf{1. 6 - T b} / \mathbf{s}$ Optical Modules
12小时前
已完结
Techniques for minimizing error propagation in decision feedback detectors for recording channels
2个月前
已完结
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver
2个月前
已完结
Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture
2个月前
已完结
Reduced complexity MLSD equalizers based on bidirectional DFEs
2个月前
已完结
Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers
2个月前
已完结
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