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550 积分 2023-11-22 加入
Digital Equalization With ADC-Based Receivers: Two Important Roles Played by Digital Signal Processingin Designing Analog-to-Digital-Converter-Based Wireline Communication Receivers
10天前
已完结
Research and implementation of clock recovery method based on software PLL
24天前
已完结
A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks
1个月前
已完结
FPGA implementation of LMS self correcting adaptive filter (SCAF) and hardware analysis
1个月前
已完结
FPGA implementation of LMS self correcting adaptive filter (SCAF) and hardware analysis
1个月前
已完结
Distributed arithmetic LMS adaptive filter implementation without look-up table
1个月前
已完结
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS
1个月前
已完结
A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver
1个月前
已完结
A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver
1个月前
已关闭
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2
1个月前
已完结
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